X-500 / X-55 Series Power Fail Protection
The X-500 and X-55 SSDs use an internal DRAM, but only management data is cached in the DRAM, no user data (as done in other SSDs). User data is always processed through the small internal controller cache directly into the flash chips.
Together with the user data, also the page mapping information is saved into the flash. The information in the DRAM is merely a copy of the management data for better performance.
Download this whitepaper to learn more.
Read More
By submitting this form you agree to Swissbit contacting you with marketing-related emails or by telephone. You may unsubscribe at any time. Swissbit web sites and communications are subject to their Privacy Notice.
By requesting this resource you agree to our terms of use. All data is protected by our Privacy Notice. If you have any further questions please email dataprotection@techpublishhub.com
Related Categories: Industrial, Power
More resources from Swissbit
X-500 / X-55 Series SLC vs. EM-MLC
Swissbit's latest SSD generation is available in 2 versions. Firstly, the X-500: based on SLC NAND flash (Single Level Cell) for applications with ...
Swissbit SSD Power Management without supercaps
Most NAND Flash based 2.5” SSDs have RAM caches for high IOPS, the contents of which take multiple write cycles (written to flash) to store safel...
Swissbit Flash Products Reliability & Data Integrity Managing Read Disturb Effects Data Retention Endurance
NAND Flash chips are organized in Pages (2…16kB+spare) and Blocks (typically 64 pages). A page can be programmed once or up to four times, but on...
